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Complete 12-Bit 40 MHz CCD Signal Processor AD9945
FEATURES 40 MSPS Correlated Double Sampler (CDS) 6 dB to 40 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Optical Black Clamp Circuit Preblanking Function 12-Bit 40 MSPS A/D Converter No Missing Codes Guaranteed 3-Wire Serial Digital Interface 3 V Single-Supply Operation Low Power: 140 mW @ 3 V Supply Space-Saving 32-Lead 5 mm 5 mm LFCSP APPLICATIONS Digital Still Cameras Digital Video Camcorders PC Cameras Portable CCD Imaging Devices CCTV Cameras GENERAL DESCRIPTION
The AD9945 is a complete analog signal processor for CCD applications. It features a 40 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9945's signal chain consists of a correlated double sampler (CDS), a digitally controlled variable gain amplifier (VGA), a black level clamp, and a 12-bit A/D converter. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input clock polarity, and power-down modes. The AD9945 operates from a single 3 V power supply, typically dissipates 140 mW, and is packaged in a space-saving 32-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB PBLK
AD9945
BAND GAP REFERENCE 6dB TO 40dB
DRVDD DRVSS 12 DOUT
CCDIN
CDS
VGA
12-BIT ADC
CLP AVDD AVSS CONTROL REGISTERS DVDD DVSS 10 CLPOB
DIGITAL INTERFACE
INTERNAL TIMING
SL
SCK
SDATA
SHP
SHD
DATACLK
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9945-SPECIFICATIONS
GENERAL SPECIFICATIONS (T
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation (DRVDD Power not Included) DRVDD Power Only (CLOAD = 20 pF) Power-Down Mode MAXIMUM CLOCK RATE
Specifications subject to change without notice.
MIN
to TMAX, AVDD = DVDD = DRVDD= 3.0 V, fSAMP = 40 MHz, unless otherwise noted.)
Min -20 -65 2.7 140 10 1.5 40 Typ Max +85 +150 3.6 Unit C C V mW mW mW MHz
DIGITAL SPECIFICATIONS (DRVDD = DVDD = 2.7 V, C = 20 pF, unless otherwise noted.)
L
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA
Specifications subject to change without notice.
Symbol VIH VIL IIH IIL CIN VOH VOL
Min 2.1
Typ
Max
Unit V V A A pF V V
0.6 10 10 10 2.2 0.5
-2-
REV. A
AD9945 SYSTEM SPECIFICATIONS (T
Parameter
CDS Maximum Input Range before Saturation* Allowable CCD Reset Transient* Maximum CCD Black Pixel Amplitude* VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Minimum Gain Maximum Gain BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level Maximum Clamp Level A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Data Output Coding Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Range Low Gain (VGA Code = 0) Maximum Gain (VGA Code = 1023) Gain Accuracy Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR)
*Input Signal Characteristics defined as follows:
MIN
to TMAX, AVDD = DVDD = DRVDD = 3.0 V, fSAMP = 40 MHz, unless otherwise noted.)
Min Typ
1.0 500 100 1024 Guaranteed 5.3 41.5
Max
Unit
Vp-p mV mV Steps
Notes
See Input Waveform in Footnote
40.0
dB dB
See Figure 7 for VGA Gain Curve See Variable Gain Amplifier Section for VGA Gain Equation
256 0 255 12 0.5 Guaranteed Straight Binary 2.0 2.0 1.0
Steps Measured at ADC Output LSB LSB Bits LSB
V V V Specifications Include Entire Signal Chain
40.0
5.3 41.5 1.0 0.1 1.2 40
dB dB dB % LSB rms dB
12 dB Gain Applied AC Grounded Input, 6 dB Gain Applied
500mV TYP RESET TRANSIENT 100mV TYP OPTICAL BLACK PIXEL 1V TYP INPUT SIGNAL RANGE
Specifications subject to change without notice.
REV. A
-3-
AD9945 TIMING SPECIFICATIONS (C = 20 pF, f
L SAMP
= 40 MHz, CCD Mode Timing in Figures 8 and 9, Serial Timing in Figures 4 and 5.)
Symbol tCONV tADC tSHP tSHD tCOB tS1 tS2 tID tOD Min 25 10 Typ Max Unit ns ns ns ns Pixels ns ns ns ns Cycles MHz ns ns ns ns
Parameter SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK High/Low Pulse Width SHP Pulse Width SHD Pulse Width CLPOB Pulse Width* SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge Internal Clock Delay DATA OUTPUTS Output Delay Pipeline Delay SERIAL INTERFACE Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold
Specifications subject to change without notice.
2 11.25
12.5 6.25 6.25 20 6.25 12.5 3 9.5 10
fSCLK tLS tLH tDS tDH
10 10 10 10 10
*Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
ABSOLUTE MAXIMUM RATINGS* With Respect To Min Max AVSS DVSS DRVSS DRVSS DVSS DVSS DVSS AVSS -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 +3.9 +3.9 +3.9 DRVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 150 300
ORDERING GUIDE
Model
Unit V V V V V V V V C C
Temperature Range -20C to +85C -20C to +85C -20C to +85C -20C to +85C -20C to +85C
Package Package Description1 Option LFCSP LFCSP LFCSP LFCSP LFCSP CP-32 CP-32 CP-32 CP-32 CP-32
Parameter AVDD DVDD DRVDD Digital Outputs SHP, SHD, DATACLK CLPOB, PBLK SCK, SL, SDATA REFT, REFB, CCDIN Junction Temperature Lead Temperature (10 sec)
AD9945KCP AD9945KCPRL AD9945KCPRL7 AD9945KCPZ2 AD9945KCPZRL72
1 2
LFCSP = Lead Frame Chip Scale Package Z = Pb-free part.
THERMAL CHARACTERISTICS
Thermal Resistance 32-Lead LFCSP Package JA = 27.7 C/W
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9945 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-4-
REV. A
AD9945
PIN CONFIGURATION
D1 D0 NC NC NC SCK SDATA SL
D2 D3 D4 D5 D6 D7 D8 D9
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
PIN 1 INDICATOR
AD9945
TOP VIEW
24 23 22 21 20 19 18 17
REFB REFT CCDIN AVSS AVDD SHD SHP CLPOB
PIN FUNCTION DESCRIPTIONS
Pin Number 1 to 10, 31, 32 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 to 30
Mnemonic D2 to D11, D0, D1 DRVDD DRVSS DVDD DATACLK DVSS PBLK CLPOB SHP SHD AVDD AVSS CCDIN REFT REFB SL SDATA SCK NC
Type DO P P P DI P DI DI DI DI P P AI AO AO DI DI DI NC
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. A
D10 9 D11 10 DRVDD 11 DRVSS 12 DVDD 13 DATACLK 14 DVSS 15 PBLK 16
Description Digital Data Outputs Digital Output Driver Supply Digital Output Driver Ground Digital Supply Digital Data Output Latch Clock Digital Supply Ground Preblanking Clock Input Black Level Clamp Clock Input CDS Sampling Clock for CCD's Reference Level CDS Sampling Clock for CCD's Data Level Analog Supply Analog Ground Analog Input for CCD Signal A/D Converter Top Reference Voltage Decoupling A/D Converter Bottom Reference Voltage Decoupling Serial Digital Interface Load Pulse Serial Digital Interface Data Input Serial Digital Interface Clock Input Internally Pulled Down. Float or connect to GND.
-5-
AD9945
DEFINITIONS OF SPECIFICATIONS Differential Nonlinearity (DNL)
at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC Full Scale/2N codes) where N is the bit resolution of the ADC. For the AD9945, 1 LSB is 0.5 mV.
Power Supply Rejection (PSR)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9945 from a true straight line. The point used as zero scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC fullscale signal. The input signal is always appropriately gained up to fill the ADC's full-scale range.
Total Output Noise
The PSR is measured with a step change applied to the supply pins. This represents a very high frequency disturbance on the AD9945's power supply. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.
Internal Delay for SHP/SHD
The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain
EQUIVALENT INPUT CIRCUITS
DVDD
The internal delay (also called aperture delay) is the delay that occurs from the time when a sampling edge is applied to the AD9945 until the actual sample of the input signal is held. Both SHP and SHD sample the input signal during the transition from low to high, so the internal delay is measured from each clock's rising edge to the instant the actual internal sample is taken.
AVDD
330
60
DVSS
AVSS
AVSS
Figure 1. Digital Inputs--SHP, SHD, DATACLK, CLPOB, PBLK, SCK, SL, SDATA
DVDD DRVDD
Figure 3. CCDIN (Pin 22)
DATA
THREESTATE
DOUT
DVSS
DRVSS
Figure 2. Data Outputs--D0 to D11
-6-
REV. A
Typical Performance Characteristics-AD9945
180
1.0
165
POWER DISSIPATION (mV)
VDD = 3.3 V 150
0.5
135
VDD = 3.0 V
DNL (LSB)
40
0
120
VDD = 2.7 V
-0.5
105
90 25 32 SAMPLE RATE (MHz)
-1.0 0 800 1600 CODE 2400 3200 4000
TPC 1. Power vs. Sampling Rate
TPC 2. Typical DNL Performance
REV. A
-7-
AD9945
INTERNAL REGISTER DESCRIPTION Table I. Internal Register Map
Register Name Operation
Address Bits A2 A1 A0 0 0 0
Data Bits D0 D2, D1 D3 D5, D4 D6 D8, D7 D11 to D9 D0 D1 D2 D3 D4 D5 D6 D11 to D7 D7 to D0 D9 to D0
Function Software Reset (0 = Normal Operation, 1 = Reset all registers to default) Power-Down Modes (00 = Normal Power, 01 = Standby, 10 = Total Shutdown) OB Clamp Disable (0 = Clamp ON, 1 = Clamp OFF) Test Mode. Should always be set to 00. PBLK Blanking Level (0 = Blank Output to Zero, 1 = Blank to OB Clamp Level) Test Mode 1. Should always be set to 00. Test Mode 2. Should always be set to 000. SHP/SHD Input Polarity (0 = Active Low, 1 = Active High) DATACLK Input Polarity (0 = Active Low, 1 = Active High) CLPOB Input Polarity (0 = Active Low, 1 = Active High) PBLK Input Polarity (0 = Active Low, 1 = Active High) Three-State Data Outputs (0 = Outputs Active, 1 = Outputs Three-Stated) Data Output Latching (0 = Latched by DATACLK, 1 = Latch is Transparent) Data Output Coding (0 = Binary Output, 1 = Gray Code Output) Test Mode. Should always be set to 00000. OB Clamp Level (0 = 0 LSB, 255 = 255 LSB) VGA Gain (0 = 6 dB, 1023 = 40 dB)
Control
0
0
1
Clamp Level VGA Gain
0 0
1 1
0 1
NOTE: All register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (128 LSB clamp level).
-8-
REV. A
AD9945
SERIAL INTERFACE
TEST BIT SDATA A0 A1 A2 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
tDS
SCK
tDH
tLS
SL
tLH
NOTES 1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE. 3. ALL 12 DATA BITS D0 TO D11 MUST BE WRITTEN. IF THE REGISTER CONTAINS FEWER THAN 12 BITS, ZEROS SHOULD BE USED FOR THE UNDEFINED BITS. 4. TEST BIT IS FOR INTERNAL USE ONLY. MUST BE SET LOW.
Figure 4. Serial Write Operation
TEST BIT SDATA A0 A1 A2 0 D0
DATA FOR STARTING REGISTER ADDRESS D1 D2 D3 D4 D5
DATA FOR NEXT REGISTER ADDRESS
... ... ...
D10
D11
D0
D1
... ... ...
D10 D11
D0
D1
D2
... ... ...
SCK
1
2
3
4
5
6
7
8
9
10
15
16
17
18
27
28
29
30
31
SL
NOTES 1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 12-BIT DATA-WORDS. 3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 12-BIT DATA-WORD (ALL 12 BITS MUST BE WRITTEN). 4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. NEW DATA IS UPDATED AT THE NEXT SL RISING EDGE.
Figure 5. Continuous Serial Write Operation to All Registers
REV. A
-9-
AD9945
DC RESTORE INTERNAL VREF 6dB TO 40dB 0.1 F CCDIN CDS VGA 2V FULL SCALE 12-BIT ADC 12 DOUT
10
8-BIT DAC
OPTICAL BLACK CLAMP
CLPOB
VGA GAIN REGISTER
DIGITAL FILTERING 8 CLAMP LEVEL REGISTER
Figure 6. CCD Mode Block Diagram
CIRCUIT DESCRIPTION AND OPERATION
The AD9945 signal processing chain is shown in Figure 6. Each processing step is essential in achieving a high quality image from the raw CCD pixel data.
DC Restore
When the loop is disabled, the clamp level register may still be used to provide programmable offset adjustment. Horizontal timing is shown in Figure 9. The CLPOB pulse should be placed during the CCD's optical black pixels. It is recommended that the CLPOB pulse be used during valid CCD dark pixels. The CLPOB pulse should be a minimum of 20 pixels wide to minimize clamp noise. Shorter pulse widths may be used, but clamp noise may increase and the loop's ability to track low frequency variations in the black level will be reduced.
A/D Converter
To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 F series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V to be compatible with the 3 V single supply of the AD9945.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the video information and reject low frequency noise. The timing shown in Figure 8 illustrates how the two CDS clocks, SHP and SHD, are used to sample the reference level and data level of the CCD signal, respectively. The CCD signal is sampled on the rising edges of SHP and SHD. Placement of these two clock signals is critical in achieving the best performance from the CCD. An internal SHP/SHD delay (tID) of 3 ns is caused by internal propagation delays.
Optical Black Clamp
The ADC uses a 2 V input range. Better noise performance results from using a larger ADC full-scale range. The ADC uses a pipelined architecture with a 2 V full-scale input for low noise performance.
Variable Gain Amplifier
The VGA stage provides a gain range of 6 dB to 40 dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. A plot of the VGA gain curve is shown in Figure 7. VGA Gain(dB) = ( VGA Code x 0.035 dB) + 5.3 dB
42
The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD's black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with the fixed black level reference, selected by the user in the clamp level register. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a D/A converter. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during the postprocessing, the AD9945 optical black clamping may be disabled using Bit D3 in the operation register (see the Serial Interface Timing and Internal Register Description sections).
36
VGA GAIN (dB)
30
24
18
12
6 0 127 255 383 511 639 767 VGA GAIN REGISTER CODE 895 1023
Figure 7. VGA Gain Curve
-10-
REV. A
AD9945
CCD MODE TIMING
CCD SIGNAL
tID
N
N+1
N+2
N+9
N+10
tID
SHP
tS1
SHD
tS2
tCP
DATACLK
tOD
OUTPUT DATA N-10 N- 9 N- 8 N- 1 N
NOTES 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
Figure 8. CCD Mode Timing
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
HORIZONTAL BLANKING
DUMMY PIXELS
EFFECTIVE PIXELS
CCD SIGNAL
CLPOB
PBLK
OUTPUT DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
DUMMY BLACK
EFFECTIVE DATA
NOTES 1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB. 2. PBLK SIGNAL IS OPTIONAL. 3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
Figure 9. Typical CCD Mode Line Clamp Timing
REV. A
-11-
AD9945
APPLICATIONS INFORMATION
The AD9945 is a complete analog front end (AFE) product for digital still camera and camcorder applications. As shown in Figure 10, the CCD image (pixel) data is buffered and sent to the AD9945 analog input through a series input capacitor. The AD9945 performs the dc restoration, CDS, gain adjustment, black
level correction, and analog-to-digital conversion. The AD9945's digital output data is then processed by the image processing ASIC. The internal registers of the AD9945--used to control gain, offset level, and other functions--are programmed by the ASIC or microprocessor through a 3-wire serial digital interface. A system timing generator provides the clock signals for both the CCD and the AFE.
CCD VOUT 0.1 F
AD9945
ADCOUT CCDIN REGISTERDATA BUFFER CDS/CLAMP TIMING CCD TIMING TIMING GENERATOR
DIGITAL OUTPUTS SERIAL INTERFACE DIGITAL IMAGE PROCESSING ASIC
V-DRIVE
Figure 10. System Applications Diagram
-12-
REV. A
AD9945
Internal Power-On Reset Circuitry
After power-on, the AD9945 will automatically reset all internal registers and perform internal calibration procedures. This takes approximately 1 ms to complete. During this time, normal clock signals and serial write operations may occur. However, serial register writes will be ignored until the internal reset operation is completed.
Grounding and Decoupling Recommendations
As shown in Figure 11, a single ground plane is recommended for the AD9945. This ground plane should be as continuous as possible. This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power
and bypass pins and their respective ground pins. All decoupling capacitors should be located as close as possible to the package pins. A single clean power supply is recommended for the AD9945, but a separate digital driver supply may be used for DRVDD (Pin 11). DRVDD should always be decoupled to DRVSS (Pin 12), which should be connected to the analog ground plane. Advantages of using a separate digital driver supply include using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing digital power dissipation, and reducing potential noise coupling. If the digital outputs (Pins 1 to 10, 31, and 32) must drive a load larger than 20 pF, buffering is recommended to reduce digital code transition noise. Alternatively, placing series resistors close to the digital output pins may also help reduce noise.
SERIAL INTERFACE D0
3
SDATA 26
SCK
NC
NC
NC
D1
32
31
30
29
28
27
25
SL
D2 D3 D4 D5 D6 D7 D8 D9
1 2 3 4 5 6 7 8
24 PIN 1 IDENTIFIER 23 22
REFB REFT CCDIN AVSS AVDD SHD SHP CLPOB
1.0 F 1.0 F 0.1 F CCDIN 3V ANALOG SUPPLY
AD9945
TOP VIEW (Not to Scale)
21 20 19 18 17
0.1 F
DRVSS 12
DVDD 13
DATACLK 14
DVSS 15
DATA OUTPUTS
12
DRVDD 11
PBLK 16
D10
D11 10
9
5
CLOCK INPUTS
3V DRIVER SUPPLY 0.1 F 0.1 F
3V ANALOG SUPPLY
NC = NO CONNECT NOTE THE EXPOSED PAD ON THE BOTTOM OF THE AD9945 SHOULD BE SOLDERED TO THE GND PLANE OF THE PRINTED CIRCUIT BOARD
Figure 11. Recommended Circuit Configuration for CCD Mode
REV. A
-13-
AD9945
OUTLINE DIMENSIONS 32-Lead Lead Frame Chip Scale Package (LFCSP) 5 mm 5 mm Body (CP-32)
Dimensions shown in millimeters
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
4.75 BSC SQ
0.50 BSC
BOTTOM VIEW
3.25 3.10 SQ 2.95
8
0.50 0.40 0.30 12 MAX 0.80 MAX 0.65 NOM 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08
17 16
9
3.50 REF
1.00 0.90 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
-14-
REV. A
AD9945 Revision History
Location 11/03--Data Sheet changed from REV. 0 to REV. A Page
Changes to TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to Figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REV. A
-15-
-16-
C03636-0-11/03(A)

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